1. Technical Field
The invention relates generally to semiconductor device fabrication, and more particularly, to a transistor structure having a recessed source/drain and buried etch stop layer, such as a silicon germanium layer, and a related method.
2. Background Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of electrical current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride liners. For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. Typically, the higher each of these stresses are, the better performance that is achieved. In order to increase each of these stresses, embedding the stress into source/drain regions is advantageous. One mechanism to provide this is to recess the source/drain regions and implement the stress into the replaced material. However, one challenge relative to this structure is not over-recessing (using too much depth of the source/drain extension region) such that the recess becomes too close or connects to the P-N junction of the source/drain region. Over-recessing causes current leakage in the device via the silicide formed in the recess. It is also important to obtain good control of the recess depth since it impacts the performance control of the device and the yield.